Method of forming shallow trench isolation (sti) structures

ABSTRACT

A method of forming a trench isolation (e.g., an STI) for an integrated circuit includes forming a pad oxide layer and then a nitride layer over a semiconductor substrate, performing a trench etch through the structure to form a trench, depositing a trench oxide layer over the structure to form a filled trench, depositing a sacrificial planarizing layer, which is etch-selective to the trench oxide layer, over the deposited oxide, performing a planarizing etch process that removes the sacrificial planarizing layer and decreases surface variations in an upper surface of the trench oxide layer, performing an oxide etch process that is selective to the trench oxide layer to remove remaining portions of the trench oxide layer outside the filled trench, and removing the remaining nitride layer such that the remaining oxide-filled trench defines a trench isolation structure that projects above an exposed upper surface of the semiconductor substrate.

TECHNICAL FIELD

The present disclosure relates to semiconductor integrated circuit (IC)fabrication, and more particularly, to methods of forming shallow trenchisolation structures (STIs), e.g., for a complementary metal-oxidesemiconductor (CMOS) device.

BACKGROUND

Shallow trench isolation (STI) is an integrated circuit feature thatprevents electrical current leakage between adjacent semiconductordevice components. STI structures are commonly used in CMOS devices, andare typically formed early during the semiconductor device fabricationprocess, before transistors are formed. The key steps of a conventionalSTI process involve etching a pattern of trenches in a siliconsubstrate, depositing one or more dielectric materials (e.g., silicondioxide) to fill the trenches, and removing the excess dielectric usingchemical-mechanical planarization (CMP).

However, the CMP processing involved in conventional STI formation maycause one or more related problems. For example, the CMP process mayproduce a significant center-to-edge bias that may result in sufficientvariation across the wafer to cause yield fallout. As another example,CMP may cause localized non-uniformity and dishing of the field oxide.Further, the CMP process may leave oxide residue on the largest activeareas, which may cause SiN residue that results in yield loss. Finally,the conventional STI formation processing using CMP involves arelatively large number of steps.

SUMMARY

According to the teachings of this disclosure, trench isolationstructures, e.g., shallow trench isolations (STIs), can be formedwithout using CMP and/or with a reduced number of steps as compared withconventional techniques.

In one embodiment, a method of forming a trench isolation structure(e.g., an STI) for an integrated circuit includes: forming a thin padoxide layer then a nitride layer over a semiconductor substrate;performing a trench etch process through portions of the nitride layer,pad oxide, and the semiconductor substrate to form a trench; depositinga trench oxide layer over remaining portions of the nitride layer andextending into the trench to form a filled trench; depositing asacrificial planarizing layer over the deposited oxide, the sacrificialplanarizing layer being etch-selective with respect to the trench oxidelayer; performing a planarizing etch process that removes thesacrificial planarizing layer and decreases surface variations in anupper surface of the trench oxide layer; performing an oxide etchprocess that is selective to the trench oxide layer to remove remainingportions of the trench oxide layer outside the filled trench; andperforming a nitride removal process that removes the remaining portionsof the nitride layer such that the remaining oxide of the filled trenchdefines a trench isolation structure that projects above an exposedupper surface of the semiconductor substrate. This technique can ofcourse be used to form a plurality of trench isolation structures asdesired.

In another embodiment, a semiconductor die may include a semiconductorsubstrate and a plurality of trench isolation structures (e.g., STIs)formed in the semiconductor substrate by a process including: forming athin pad oxide layer then a nitride layer over the semiconductorsubstrate; performing a trench etch process through portions of thenitride layer, pad oxide, and the semiconductor substrate to form aplurality of trenches; depositing a trench oxide layer over remainingportions of the nitride layer and extending into the trenches to form aplurality of filled trenches; depositing a sacrificial planarizing layerover the deposited oxide, the sacrificial planarizing layer beingetch-selective with respect to the trench oxide layer; performing aplanarizing etch process that removes the sacrificial planarizing layerand decreases surface variations in an upper surface of the trench oxidelayer; performing an oxide etch process that is selective to the trenchoxide layer to remove remaining portions of the trench oxide layeroutside the filled trenches; and performing a nitride removal processthat removes the remaining portions of the nitride layer such that theremaining oxide of each filled trench defines a trench isolationstructure that projects above an exposed upper surface of thesemiconductor substrate.

In other embodiments, a CMOS device comprises a semiconductor structureincluding a plurality of trench isolation structures formed as discussedabove.

In some embodiments, the sacrificial planarizing layer comprises anorganosilicate. In particular embodiments, the sacrificial planarizinglayer comprises an organo-siloxane based polymer, e.g., according to thechemical formula R_(x)CH_(3y)SiO_(z), where R is an organic chromophore.For example, in some embodiments the sacrificial planarizing layer maycomprise a DUO™193 or DUO™248 anti-reflective coating supplied byHoneywell Electronic Materials, having a location at 101 Columbia Rd,Morristown, N.J. 07960.

BRIEF DESCRIPTION OF THE FIGURES

Example embodiments are discussed below with reference to the drawings,in which:

FIGS. 1A-1H illustrate a cross-section of an example semiconductorintegrated circuit structure, showing a step-by-step process of formingtrench isolation structures (e.g., STIs) for an integrated circuit,according to an example embodiment of the invention;

FIG. 2 is a flowchart of an example method of forming shallow trenchisolations for an integrated circuit, e.g., CMOS device, correspondingto the process illustrated in FIGS. 1A-1H, according to an exampleembodiment;

FIGS. 3A-3H illustrate a cross-section of another example semiconductorintegrated circuit structure, showing a step-by-step process of formingtrench isolation structures (e.g., STIs) for an integrated circuit,according to an example embodiment of the invention; and

FIG. 4 is a flowchart of an example method of forming shallow trenchisolations for an integrated circuit, e.g., CMOS device, correspondingto the process illustrated in FIGS. 3A-3H, according to an exampleembodiment.

DETAILED DESCRIPTION

According to the teachings of this disclosure, trench isolationstructures, e.g., shallow trench isolations (STIs), can be formedwithout using CMP and/or with a reduced number of steps as compared withconventional techniques. Such process may reduce or eliminate one ormore problems related to CMP processing, and/or may reduce cost andcomplexity of forming STIs.

Referring now to the drawings, the details of specific exampleembodiments are schematically illustrated. Like elements in the drawingswill be represented by like numbers, and similar elements will berepresented by like numbers with a different lower case letter suffix.

FIGS. 1A-1H illustrate the steps of an example process of forming trenchisolation structures (e.g., STIs) for an integrated circuit, e.g., aCMOS device, according to an example embodiment.

As shown in FIG. 1A, an integrated circuit structure 10 includes asemiconductor substrate 12, e.g., a silicon (Si) substrate, formed on awafer surface. An oxide layer 13, e.g., a thin pad oxide layer ofsilicon dioxide (SiO₂), is formed or deposited over the semiconductorsubstrate 12 to help stress/adhesion of the nitride to the substrate. Anitride layer 16, e.g., silicon nitride (SiN), is deposited over the padoxide layer 13, and a trench etch process, e.g., an STI etch, isperformed through portions of the nitride layer 16, pad oxide layer 13,and the semiconductor substrate 12 to form one or more trenches 20,using any suitable photolithography techniques. The oxide layer 13 maybe formed or deposited prior to the nitride layer 16 to helpstress/adhesion of the nitride to the substrate, and may have athickness of about 1/10 the thickness of the deposited nitride layer 16.After the etch, a liner oxidation may form a liner oxide layer 14 on theexposed surfaces of the semiconductor substrate 12.

As shown in FIG. 1B, a trench oxide layer 24, e.g., silicon dioxide(SiO₂), is deposited over the structure, and extends into each trench 20to form filled trenches. In some embodiments, the trench oxide layer 24is deposited by High-Density Plasma Chemical Vapor Deposition (HDP CVD).As shown, the deposited trench oxide layer 24 may have a non-planartopography, e.g., due to the topography of the underlying structure. Inparticular, the topography of the trench oxide layer 24 may define anumber of upwardly protruding or extending features or regions 26.

As shown in FIG. 1C, a sacrificial planarizing layer 30 is depositedover the trench oxide layer 24. The sacrificial planarizing layer 30 isetch-selective with respect to the trench oxide layer 24. In someembodiments, the planarizing layer comprises an organosilicate. Forexample, the planarizing layer 30 may comprise an organo-siloxane basedpolymer, e.g., an organo-siloxane based polymer with the chemicalformula R_(x)CH_(3y)SiO_(z), where R is an organic chromophore. Inexample embodiments, the sacrificial planarizing layer 30 comprises aDUO™193 or DUO™248 anti-reflective coating supplied by HoneywellElectronic Materials, having a location at 101 Columbia Rd, Morristown,N.J. 07960. The planarizing layer 30 may be deposited in any suitablemanner. In some embodiments, planarizing layer 30 is spin-coated overthe trench oxide layer 24, which provides a partially planarizingeffect.

A planarizing etch process is then performed to remove the sacrificialplanarizing layer 30 and decrease surface variations in the uppersurface of the trench oxide layer 24, e.g., by reducing or eliminatingthe upwardly protruding or extending features or regions 26. Theplanarizing etch process may include a single etch process or a seriesof different etch processes. In the example discussed below, theplanarizing etch process shown in FIGS. 1D and 1E involves threedifferent etches.

Referring to FIG. 1D, the wafer is etched in an oxide etcher, first witha tuned etch to open the planarizing layer, and then with a short oxideetch selective to the trench oxide layer 24. The second etch will causethe upwardly projecting oxide areas 26 to be etched, while the lowerfield areas of the oxide layer 24 are protected by the sacrificialplanarizing layer 30. In one embodiment, the second etch is stopped whenthe highest points 26 are about level with the bulk planarizing layer30.

In the present document, an etch process that etches through a firstsubstance/layer faster than a second substance/layer is said to be“selective to” the first substance/layer over the secondsubstance/layer.

Referring to FIG. 1E, a third etch is then performed, which isnon-selective with respect to the trench oxide layer 24 and sacrificialplanarizing layer 30, to remove the trench oxide layer 24 andsacrificial planarizing layer 30 at similar rates, until the planarizinglayer 30 is removed. This etch may be stopped before reaching thenitride layer 16, as shown in FIG. 1E.

As shown in FIG. 1F, an oxide etch that is highly selective to thetrench oxide layer 24 is then performed to remove remaining portions ofthe trench oxide layer 24 outside the filled trenches 20, therebydefining a field oxide 40 in each trench 20. In some embodiments, adefined amount of over-etch is performed, which may trench the fieldoxides 40 and clear any residue on the remaining nitride layer 16.

As shown in FIG. 1G, an optional wet etch is performed to remove oxideresidue on the nitride layer 16 and/or to control the height of thefield oxides 40. The wet etch may be designed to provide a definedheight of the field oxides 40 relative to the top of the substrate 12,indicated as distance D₁ in FIG. 1G, which height may be selected inorder to provide a final height of the field oxides 40, indicated asdistance D₂ in FIG. 1H, based on knowledge of the height-reductionassociated with subsequent processing steps.

As shown in FIG. 1H, the nitride layer 16 is then removed using anysuitable removal process, e.g., by an etch selective to the nitridelayer 16 over the materials of the field oxide 40 and substrate 12. Asshown, the remaining field oxides 40, i.e., trench isolation structures,may project above the exposed upper surface of the semiconductorsubstrate 12 by a targeted step height indicated at D₂, i.e., the heightof the top surface of field oxide 40 relative to the top surface 52 ofsubstrate 12. In some embodiments, step height D₂ and/or top shape offield oxides 40 may be controlled as desired by performing any suitableprocesses, e.g., plasma etch, wet etch, or by running a long wet removalprocess (e.g., wet SiN removal) to remove the remaining portions of thenitride layer 16.

Thus, in some embodiments, the trench isolation structures 40 (e.g.,STIs) may be formed without using any chemical-mechanical planarization(CMP) process, which may provide various advantages as discussed above.The nitride removal step may also be performed in-situ with the rest ofthe planarizing etches, if the optional wet etch is skipped, therebyfurther reducing the total number of steps.

FIG. 2 is a flowchart of an example method 100 of forming shallow trenchisolations for an integrated circuit, e.g., CMOS device, according to anexample embodiment corresponding to FIGS. 1A-1H. At step 102, a siliconsubstrate is formed on a wafer. At step 104, a pad oxidation processforms a pad oxide over the surface of the silicon substrate. At step106, a silicon nitride layer is deposited over the silicon substrate. Atstep 108, a trench etch, e.g., an STI etch, is performed to form aplurality of trenches. At step 109, a liner oxidation process forms aliner oxide in the formed trenches. At step 110, a silicon dioxide layer(trench oxide layer) is deposited over the wafer by High-Density PlasmaChemical Vapor Deposition (HDP CVD), which fills the etched trenches.The deposited silicon dioxide layer may have a non-planar topography,e.g., due to the topography of the underlying structure. In particular,the silicon dioxide layer may define a number of upwardly protruding orextending features or regions.

At step 112, a sacrificial planarizing layer of an organo-siloxane basedpolymer (e.g., DUO™193 or DUO™248) is deposited over the silicon dioxidelayer. At step 114, a tuned etch is performed to open the sacrificialplanarizing layer, followed by a short oxide etch selective to thesilicon dioxide layer at step 116. The etch at step 116 may at leastpartially etch the upwardly projecting areas of the silicon dioxide,while the lower areas of silicon dioxide are protected by thesacrificial planarizing layer. At step 118, a non-selective etch isperformed to etch through the silicon dioxide layer and sacrificialplanarizing layer at similar rates, until the sacrificial planarizinglayer is removed. This etch may be stopped before reaching theunderlying silicon nitride layer.

At step 120, an oxide etch that is highly selective to silicon dioxideis then performed to remove portions of the silicon dioxide layer aboveand outside the filled trenches, thereby defining a field oxide in eachtrench. In some embodiments, a defined amount of over-etch is performed,which may trench the field oxides and clear any residue on the remainingsilicon nitride layer. At step 122, an optional wet etch is performed toremove oxide residue on the remaining silicon nitride layer and/or tocontrol the height of the field oxides. At step 124, the silicon nitridelayer is removed using any suitable removal process, e.g., an etchselective to silicon nitride over the silicon dioxide field oxide andthe silicon substrate. The remaining field oxides, i.e., trenchisolation structures, may project above the exposed upper surface of thesilicon substrate by a targeted step height, which may be controlled orshaped as desired using any suitable finishing process(es).

Thus, in this manner, shallow trench isolations may be formed withoutusing any chemical-mechanical planarization (CMP) process, which mayprovide various advantages as discussed above.

FIGS. 3A-3H illustrate the steps of another example embodiment of aprocess for forming trench isolation structures (e.g., STIs) for anintegrated circuit, e.g., a CMOS device.

The initial steps of the process may be similar to those of theembodiment discussed above. Thus, the steps corresponding to FIGS. 3A-3Cmay be similar to those of FIGS. 1A-1C discussed above.

As shown in FIG. 3A, an integrated circuit structure 10 includes asemiconductor substrate 12, e.g., a silicon (Si) substrate, formed on awafer surface. An oxide layer 13, e.g., a thin pad oxide layer ofsilicon dioxide (SiO₂), is formed or deposited over the semiconductorsubstrate 12 to help stress/adhesion of the nitride to the substrate. Anitride layer 16, e.g., silicon nitride (SiN), is deposited over the padoxide layer 13, and a trench etch process, e.g., an STI etch, isperformed through portions of the nitride layer 16, pad oxide layer 13,and the semiconductor substrate 12 to form one or more trenches 20,using any suitable photolithography techniques, e.g., as discussed abovewith reference to FIG. 1A. After the etch, a liner oxidation may form aliner oxide layer 14 on the exposed surfaces of the semiconductorsubstrate 12.

As shown in FIG. 3B, a trench oxide layer 24, e.g., silicon dioxide(SiO₂), is deposited over the structure, and extends into each trench 20to form filled trenches. In some embodiments, the trench oxide layer 24is deposited by High-Density Plasma Chemical Vapor Deposition (HDP CVD).As shown, the deposited trench oxide layer 24 may have a non-planartopography, e.g., due to the topography of the underlying structure. Inparticular, the topography of the trench oxide layer 24 may define anumber of upwardly protruding or extending features or regions 26.

As shown in FIG. 3C, a sacrificial planarizing layer 30 is depositedover the trench oxide layer 24. The sacrificial planarizing layer 30 isetch-selective with respect to the trench oxide layer 24. In someembodiments, the planarizing layer comprises an organosilicate. Forexample, the planarizing layer 30 may comprise an organo-siloxane basedpolymer, e.g., an organo-siloxane based polymer with the chemicalformula R_(x)CH_(3y)SiO_(z), where R is an organic chromophore. Inexample embodiments, the sacrificial planarizing layer 30 comprises aDUO™193 or DUO™248 anti-reflective coating, e.g., as discussed abovewith reference to FIG. 1A. The planarizing layer 30 may be deposited inany suitable manner. In some embodiments, planarizing layer 30 isspin-coated over the trench oxide layer 24, which provides a partiallyplanarizing effect.

A series of etches are then performed to form the trench isolationstructures in the trenches 20, as discussed below, which in the processof forming the trench isolation structures, removes the sacrificialplanarizing layer 30 and decrease surface variations in the uppersurface of the trench oxide layer 24, e.g., by reducing or eliminatingthe upwardly protruding or extending features or regions 26.

Referring to FIG. 3D, a generally non-selective etch (e.g., which, inembodiments that use a DUI™ coating, may be referred to as a DUO etch)is performed, which etches the trench oxide layer 24 and sacrificialplanarizing layer 30, e.g., DUO™ coating (and nitride layer 16, ifrelevant) at the same or about the same rate. This generallynon-selective etch may leave portions of the sacrificial planarizinglayer 30 in low lying areas of the structure, e.g., above trenches 20,as shown in FIG. 3D. The etch may remove portions of the upwardlyprojecting oxide areas 26 of the trench oxide layer 24, while the lowerfield areas of the oxide layer 24 are protected by the sacrificialplanarizing layer 30. In one embodiment, the second etch is stopped whenthe highest points 26 are about level with the bulk planarizing layer30.

Referring to FIG. 3E, an oxide etch is performed that is selective tothe trench oxide layer 24 over the sacrificial planarizing layer 30 andnitride layer 16. As shown, the oxide etch may leave sacrificialplanarizing layer 30 over the trench areas, while regions 26 shown inFIG. 3D (e.g., above regions of nitride layer 16) are etched to a depthbelow the regions of sacrificial planarizing layer 30.

Referring to FIG. 3F, a second non-selective or generally non-selectiveclean-up etch is then performed, which may planarize and remove theremaining sacrificial planarizing layer 30 from all areas, in particularover the trenches 20 (field oxide). In some embodiments this etch may bestopped before reaching the nitride layer 16, as shown in FIG. 3E.

As shown in FIG. 3G, an oxide etch that is selective to the trench oxidelayer 24 over the sacrificial planarizing layer 30 and nitride layer 16is then performed to remove remaining portions of the trench oxide layer24 outside the filled trenches 20, thereby defining a field oxide 40 ineach trench 20. In some embodiments, a defined amount of over-etch isperformed, which may trench the field oxides 40, thereby setting thefinal field oxide height, and clear any residue on the remaining nitridelayer 16.

As shown in FIG. 3H, the nitride layer 16 is then removed using anysuitable removal process, e.g., by an etch selective to the nitridelayer 16 over the materials of the field oxide 40 and substrate 12(e.g., an SiN etch). As shown, the remaining field oxides 40, i.e.,trench isolation structures, may project above the exposed upper surfaceof the semiconductor substrate 12 by a targeted step height indicated atD₂, i.e., the height of the top surface of field oxide 40 relative tothe top surface 52 of substrate 12. In some embodiments, step height D₂and/or top shape of field oxides 40 may be controlled as desired byperforming any suitable processes, e.g., plasma etch, wet etch, or byrunning a long wet removal process (e.g., wet SiN removal) to remove theremaining portions of the nitride layer 16.

Thus, in some embodiments, the trench isolation structures 40 (e.g.,STIs) may be formed without using any chemical-mechanical planarization(CMP) process, which may provide various advantages as discussed above.The nitride removal step may also be performed in-situ with the rest ofthe planarizing etches, if the optional wet etch is skipped, therebyfurther reducing the total number of steps.

In some embodiments in which the oxide etch shown in FIG. 3G is skippedor is included in the planarizing etch process, the final nitride etchshown in FIG. 3H can be completed in-situ with the planarizing etchprocess.

FIG. 4 is a flowchart of an example method 200 of forming shallow trenchisolations for an integrated circuit, e.g., CMOS device, according to anexample embodiment corresponding to FIGS. 3A-3H.

Steps 202-210 At step 202, a silicon substrate is formed on a wafer. Atstep 204, a pad oxidation process forms a pad oxide over the surface ofthe silicon substrate. At step 206, a silicon nitride layer is depositedover the silicon substrate. At step 208, a trench etch, e.g., an STIetch, is performed to form a plurality of trenches. At step 209, a lineroxidation process forms a liner oxide in the formed trenches. At step210, a silicon dioxide layer (trench oxide layer) is deposited over thewafer by High-Density Plasma Chemical Vapor Deposition (HDP CVD), whichfills the etched trenches. The deposited silicon dioxide layer may havea non-planar topography, e.g., due to the topography of the underlyingstructure. In particular, the silicon dioxide layer may define a numberof upwardly protruding or extending features or regions.

At step 112, a sacrificial planarizing layer of an organo-siloxane basedpolymer (e.g., DUO™193 or DUO™248) is deposited over the silicon dioxidelayer. At step 214, a non-selective etch (e.g., DUO etch) is performedto remove tall or upwardly projecting regions of silicon dioxide layerand to remove a partial depth of the sacrificial planarizing layer. Theetch at step 214 may at least partially etch the upwardly projectingareas of the silicon dioxide, while the lower areas of silicon dioxideare protected by the sacrificial planarizing layer. At step 216, aselective oxide etch is performed to etch portions of silicon dioxidelayer to a depth below the remaining sacrificial planarizing layer. Atstep 218, a non-selective “clean-up” etch is performed to planarize thestructure and remove any remaining portions of sacrificial planarizinglayer, in particular over the trenches (field oxide). This etch may bestopped before reaching the underlying silicon nitride layer.

At step 220, an oxide etch that is highly selective to silicon dioxideis then performed to remove portions of the silicon dioxide layer aboveand outside the filled trenches, thereby defining a field oxide in eachtrench. In some embodiments, a defined amount of over-etch is performed,which may trench the field oxides and clear any residue on the remainingsilicon nitride layer. At step 224, the silicon nitride layer is removedusing any suitable removal process, e.g., SiN etch selective to siliconnitride over the silicon dioxide field oxide and the silicon substrate.The remaining field oxides, i.e., trench isolation structures, mayproject above the exposed upper surface of the silicon substrate by atargeted step height, which may be controlled or shaped as desired usingany suitable finishing process(es).

Thus, in this manner, shallow trench isolations may be formed withoutusing any chemical-mechanical planarization (CMP) process, which mayprovide various advantages as discussed above.

Although the disclosed embodiments are described in detail in thepresent disclosure, it should be understood that various changes,substitutions and alterations can be made to the embodiments withoutdeparting from their spirit and scope.

1-15. (canceled)
 16. A semiconductor die, comprising: a semiconductorsubstrate; and a plurality of trench isolation structures formed in thesemiconductor substrate by a process including: forming a nitride layerover the semiconductor substrate; performing a trench etch processthrough portions of the nitride layer and the semiconductor substrate toform a plurality of trenches; depositing a trench oxide layer overremaining portions of the nitride layer and extending into the pluralityof trenches to form a plurality of filled trenches; depositing asacrificial planarizing layer over the deposited oxide, the sacrificialplanarizing layer being etch-selective with respect to the trench oxidelayer; performing a multi-step etch process that: removes thesacrificial planarizing layer and decreases surface variations in anupper surface of the trench oxide layer; and removes remaining portionsof the trench oxide layer outside the plurality of filled trenches; andremoving the remaining portions of the nitride layer such that theremaining oxide of each filled trench defines a trench isolationstructure that projects above an exposed upper surface of thesemiconductor substrate.
 17. The semiconductor die according to claim16, wherein multi-step etch process comprises: (c) a planarizing etchprocess that removes the sacrificial planarizing layer and decreasessurface variations in an upper surface of the trench oxide layer; and(d) an oxide etch process that is selective to the trench oxide layer toremove remaining portions of the trench oxide layer outside the filledtrench.
 18. The semiconductor die according to claim 17, wherein theplanarizing etch process includes: a first etch that is selective to theplanarizing layer over the trench oxide layer; a second etch that isselective to the trench oxide layer over the planarizing layer; and athird etch that is less selective than the first etch, wherein thesecond etch removes the trench oxide layer and the planarizing layer atsimilar rates until the planarizing layer is removed.
 19. Thesemiconductor die according to claim 17, wherein the oxide etch processis performed until a top surface of the oxide-filled trench is etcheddown to a predefined distance below a top surface of the remainingportions of the nitride layer adjacent the oxide-filled trench.
 20. Thesemiconductor die according to claim 17, wherein the oxide etch processis performed until a top surface of the oxide-filled trench is etcheddown to a predefined distance above a top surface of the semiconductorsubstrate adjacent the oxide-filled trench.
 21. The semiconductor dieaccording to claim 16, wherein: the multi-step etch process comprises amulti-step planarizing etch process; and the step of removing theremaining portions of the nitride layer is performed by the multi-stepplanarizing etch process.
 22. The semiconductor die according to claim21, wherein multi-step etch process comprises a four-step planarizingetch process.
 23. The semiconductor die according to claim 21, whereinthe multi-step planarizing etch process includes an etch selective tooxide which is performed until a top surface of the oxide-filled trenchis etched down to a predefined distance above a top surface of thesemiconductor substrate adjacent the oxide-filled trench.
 24. Thesemiconductor die according to claim 16, wherein the planarizing layercomprises an organo-siloxane based polymer.
 25. The semiconductor dieaccording to claim 16, wherein the organosilicate comprises anorgano-siloxane based polymer with the chemical formula RxCH3ySiOz,where R is an organic chromophore.
 26. The semiconductor die accordingto claim 16, wherein the method is performed without achemical-mechanical planarization (CMP) process.
 27. A complementarymetal-oxide semiconductor (CMOS) device comprising: a semiconductorstructure comprising: a semiconductor substrate; and a plurality oftrench isolation structures formed in the semiconductor substrate by aprocess including: forming a nitride layer over the semiconductorsubstrate; performing a trench etch process through portions of thenitride layer and the semiconductor substrate to form a plurality oftrenches; depositing a trench oxide layer over remaining portions of thenitride layer and extending into the plurality of trenches to form aplurality of filled trenches; depositing a sacrificial planarizing layerover the deposited oxide, the sacrificial planarizing layer beingetch-selective with respect to the trench oxide layer; performing amulti-step etch process that: removes the sacrificial planarizing layerand decreases surface variations in an upper surface of the trench oxidelayer; and removes remaining portions of the trench oxide layer outsidethe plurality of filled trenches; and removing the remaining portions ofthe nitride layer such that the remaining oxide of each filled trenchdefines a trench isolation structure that projects above an exposedupper surface of the semiconductor substrate.
 28. The CMOS deviceaccording to claim 27, wherein the planarizing layer comprises anorgano-siloxane based polymer.